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M
FEATURES
24LC32A MODULE
ISO MODULE LAYOUT
32K I2CTM Serial EEPROM in ISO Micromodule
* ISO 7816 compliant contact locations * Single supply with operation down to 2.5V - Maximum write current 3 mA at 6.0V - Maximum read current 150 A at 6.0V - Standby current 1 A max at 2.5V * Two wire serial interface bus, I2CTM compatible * 100 kHz (2.5V) and 400 kHz (5V) compatibility * Self-timed ERASE and WRITE cycles * Power on/off data protection circuitry * 1,000,000 ERASE/WRITE cycles guaranteed * 32 byte page or byte write modes available * Schmitt trigger inputs for noise suppression * Output slope control to eliminate ground bounce * 2 ms typical write cycle time, byte or page * Electrostatic discharge protection > 4000V * Data retention > 200 years * 8-pin PDIP and SOIC packages * Temperature ranges: - Commercial: 0C to +70C
VDD
VSS
SCL
SDA
DESCRIPTION
The Microchip Technology Inc. 24LC32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM in an ISO micromodule for use in smart card applications. The device has a page-write capability of up to 32 bytes.
BLOCK DIAGRAM
HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
I/O
SCL
YDEC
SDA VCC VSS
SENSE AMP R/W CONTROL
I2C is a trademark of Philips Corporation.
(c) 1997 Microchip Technology Inc.
DS21225A-page 1
24LC32A MODULE
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VCC ........................................................................7.0V All inputs and outputs w.r.t. VSS ......-0.6V to VCC +1.0V Storage temperature .......................... -65C to +150C Ambient temp. with power applied...... -65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins ..................................... 4 kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
TABLE 1-1:
Name VSS SDA SCL VCC
PIN FUNCTIONS
Function Ground Serial Data Serial Clock +2.5V to 6.0V Power Supply
TABLE 1-2:
DC CHARACTERISTICS
Vcc = +2.5V to 6.0V Commercial (C):Tamb = 0C to +70C Parameter SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current VIH VIL VHYS VOL ILI ILO CIN,COUT ICC Write ICC Read ICCS ICCS Note 1: This parameter is periodically sampled and not 100% tested. .7 VCC -- .05 VCC -- -10 -10 -- -- -- -- 1A -- .3 Vcc -- .40 10 10 10 3 400 5 1 V V V V A A pF mA A A A Note 1 IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note 1) Tamb = 25C, fc = 1 MHz VCC = 6.0V VCC = 6.0V, SCL = 400Khz SCL = SDA = VCC = 5.0V VCC = 2.5V (Note 1) Symbol Min Typ Max Units Conditions
DS21225A-page 2
(c) 1997 Microchip Technology Inc.
24LC32A MODULE
TABLE 1-3:
Parameter
Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time
AC CHARACTERISTICS
Symbol
FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF TOF TSP
Vcc = 2.5 - 6.0V STD. MODE Min
-- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 -- --
Vcc = 4.5 - 6.0V FAST MODE Min
-- 600 1300 -- -- 600 600 0 100 600 -- 1300 20 +0.1CB --
Units
kHz ns ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Note 1
Remarks
Max
100 -- -- 1000 300 -- -- -- -- -- 3500 -- 250 50
Max
400 -- -- 300 300 -- -- -- -- -- 900 -- 250 50
After this period the first clock pulse is generated Only relevant for repeated START condition
Time the bus must be free before a new transmission can start Note 1, CB 100 pF Note 3
TWR
--
5
--
5
ms
Byte or Page mode
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
FIGURE 1-1:
BUS TIMING DATA
TF THIGH TLOW TR
SCL TSU:STA SDA IN THD:DAT TSP TAA SDA OUT THD:STA TAA TBUF TSU:DAT TSU:STO
(c) 1997 Microchip Technology Inc.
DS21225A-page 3
24LC32A MODULE
2.0
2.1
PIN DESCRIPTIONS
SDA (Serial Data)
3.0
FUNCTIONAL DESCRIPTION
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10K for 100 kHz, 1K for 400 kHz) For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
The 24LC32A supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC32A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.
2.2
SCL (Serial Clock)
This input is used to synchronize the data transfer from and to the device.
DS21225A-page 4
(c) 1997 Microchip Technology Inc.
24LC32A MODULE
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (See Figure 4-1). The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.
4.5
Acknowledge
4.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24LC32A does not generate any acknowledge bits if an internal programming cycle is in progress.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
4.4
Data Valid (D)
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC32A) will leave the data line HIGH to enable the master to generate the STOP condition. (See Figure 4-2)
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.
FIGURE 4-1:
(A) SCL (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SDA
START CONDITION
DATA OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL SDA
1
2
3
4
5
6
7
8
9
1
2
3
Data from transmitter
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
(c) 1997 Microchip Technology Inc.
DS21225A-page 5
24LC32A MODULE
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the start condition from the master device. (See Figure 51) The control byte consists of a four bit control code; for the 24LC32A this is set as 1010 binary for read and write operations. The next three bits are device select bits on standard devices, however, for micromodules, these must be zeros. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (see Figure 5-2). Because only A11...A0 are used, the upper four address bits must be zeros. The most significant bit of the most significant byte of the address is transferred first. Following the start condition, the 24LC32A monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a valid control byte, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC32A will select a read or write operation
FIGURE 5-1:
CONTROL BYTE FORMAT
Read/Write Bit Device Select Bits 0 0 0 0 R/W ACK
Control Code S 1 0 1
Slave Address Start Bit Acknowledge Bit
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
ADDRESS BYTE 1
CONTROL BYTE
ADDRESS BYTE 0
1
0
1
0
0
0
0 R/W
0
0
0
0
A 11
A 10
A 9
A 8
A 7
*
*
*
*
*
*
A 0
Slave Address
Device Select Bus
DS21225A-page 6
(c) 1997 Microchip Technology Inc.
24LC32A MODULE
6.0
6.1
WRITE OPERATIONS
Byte Write
6.2
Page Write
Following the start condition from the master, the control code (four bits), the device select (three bits), and the R/W bit which is a logic low are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24LC32A MODULE. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24LC32A the master device will transmit the data word to be written into the addressed memory location. The 24LC32A acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC32A will not generate acknowledge signals (see Figure 6-1).
The write control byte, word address and the first data byte are transmitted to the 24LC32A in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 32 bytes which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the five lower address pointer bits are internally incremented by one. If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received, an internal write cycle will begin. (see Figure 6-2).
FIGURE 6-1:
BYTE WRITE
S T A R T S T O P
BUS ACTIVITY MASTER
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
DATA
SDA LINE BUS ACTIVITY
101 0 0 000 A C K
0000 A C K A C K A C K
FIGURE 6-2:
BUS ACTIVITY MASTER
PAGE WRITE
S T A R T S T O P
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
DATA BYTE 0
DATA BYTE 31
SDA LINE BUS ACTIVITY
101 0 0 000 A C K
0000 A C K A C K A C K A C K
(c) 1997 Microchip Technology Inc.
DS21225A-page 7
24LC32A MODULE
7.0 ACKNOWLEDGE POLLING 8.0 READ OPERATION
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram. Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.
8.1
Current Address Read
FIGURE 7-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The 24LC32A contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC32A issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC32A discontinues transmission (see Figure 8-1).
8.2
Random Read
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC32A as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC32A will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24LC32A to discontinue transmission (see Figure 8-2).
FIGURE 8-1:
CURRENT ADDRESS READ
S T A R T S T O P
BUS ACTIVITY MASTER SDA LINE
CONTROL BYTE
DATA BYTE
S1 01 00001
BUS ACTIVITY A C K N O A C K
P
DS21225A-page 8
(c) 1997 Microchip Technology Inc.
24LC32A MODULE
8.3 Sequential Read
Sequential reads are initiated in the same way as a random read except that after the 24LC32A transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24LC32A to transmit the next sequentially addressed 8 bit word (see Figure 83). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a stop condition. To provide sequential reads the 24LC32A contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 0FFF to address 000 if the master acknowledges the byte received from the array address 0FFF.
FIGURE 8-2:
RANDOM READ
S T A R T S T A R T S T O P
BUS ACTIVITY MASTER
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
CONTROL BYTE
DATA BYTE
SDA LINE BUS ACTIVITY
S1 01 00000 A C K
0000 A C K A C K
S1 01 00001 A C K N O A C K
FIGURE 8-3:
SEQUENTIAL READ
S T O P
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
CONTROL BYTE
DATA n
DATA n +1
DATA n +2
DATA n + X
A C K
A C K
A C K
A C K
N O A C K
(c) 1997 Microchip Technology Inc.
DS21225A-page 9
24LC32A MODULE
9.0 SHIPPING METHOD
The micromodules will be shipped to customers in clear plastic trays. Each tray holds 150 modules, and the trays can be stacked in a manner similar to shipping die in waffle packs. A tray drawing with dimensions is shown in Figure 9-1.
FIGURE 9-1:
TRAY DIMENSIONS
9.374 [238.09]
8.145 [206.88]
0.980 [24.89] TYP
0.860 [21.84] TYP.
0.500 [12.70]
SMART CARD MODULES
ANTISTATIC
R 0.300 [7.62] TYP
R 0.270 [6.86] TYP
0.617 [15.68]
0.905 [22.99]
DS21225A-page 10
(c) 1997 Microchip Technology Inc.
12.040 [305.82]
14.000 [355.60]
FIGURE 9-2:
DEVICE SIDE
0.465 0.002 [11.80 0.05] 0.285 [7.24] MAX R. 0.059 [1.50] (4X) VIA HOLES (8x) I.D. 0.026 [0.66] O.D. 0.042 [1.06] 0.146 0.002 [3.71 0.05] 0.174 0.002 [4.42 0.05]
(c) 1997 Microchip Technology Inc.
0.1043 0.002 [2.65 0.05] TYP.
0.090 [2.29] MIN EPOXY FREE AREA (TYP.)
MODULE DIMENSIONS
0.270 [6.86] MAX.
0.419 0.002 [10.63 0.05]
A
A
0.209 0.002 [5.31 0.05] 0.1043 0.002 [2.65 0.05] (8x)
0.232 0.002 [5.90 0.05] DIE GLOB SIZE 0.0235 [0.60] MAX. 0.015 [0.38] MAX. 0.004 [0.10] MAX.
CONTACT SIDE
SECTION A-A
FR4 TAPE
0.007 [0.18] MAX.
COPPER BASE NICKEL PLATED, 150 GOLD FLASH 3-7 m IN MIN
24LC32A MODULE
DS21225A-page 11
m
IN
24LC32A MODULE
NOTES:
DS21225A-page 12
(c) 1997 Microchip Technology Inc.
24LC32A MODULE
NOTES:
(c) 1997 Microchip Technology Inc.
DS21225A-page 13
24LC32A MODULE
NOTES:
DS21225A-page 14
(c) 1997 Microchip Technology Inc.
24LC32A MODULE
24LC32A MODULE PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 24LC32A -- /MT Package: Temperature Range: Device: MT = Micromodules in trays
Blank = 0C to +70C 24LC32A 32K bit 2.5V I 2C Serial EEPROM in ISO Module
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
(c) 1997 Microchip Technology Inc.
DS21225A-page 15
M
WORLDWIDE SALES & SERVICE
AMERICAS
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All rights reserved. (c) 1997, Microchip Technology Incorporated, USA. 9/97
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21225A-page 16
(c) 1997 Microchip Technology Inc.

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